ST2202
256KB ROM Microcontroller
Product Description
The ST2202 is an design to support high-level of system functions.
It keeps the low power design and higher system-functions as before.
ST2202 is an improvement in system speed. ( X2 speed compared with ST21xx family.)
LCD controller is design in.
Flexible display window size is S/W progammable. Vertial screen is also supported.
Communications function is added. Full features of UART, IRDA and SPI are supported by H/W.
PSG is enhanced with dedicated output buffers.
Low voltage detection is designed to reduce H/W cost.
With all these integrated functions inside, the ST2202 single chip
microcontroller is a right solution for PDA, translator, databank
and other portable consumer products.
Features - 8-bit static CPU
- ROM: 256K x 8-bit
- RAM: 4K x 8-bit
- Stack: Up to 128-level deep
- Operation voltage: 2.4V ~ 5.5V
- Operation frequency:
- 3.0Mhz@2.4V(Min.)
- 4.0Mhz@2.7V(Min.)
- Low Voltage Detector (LVD)
- Memory interface to ROM, RAM, Flash
- LCD Controller (LCDC)
- Software programmable screen size up to 1024 SEGs or 512 COMs. (example SEGxCOM: 240X120, 160x160, 160x80, etc.)
- Support 1-, 4-bit LCD data bus
- Share system memory with display memory
- Unique internal bus for memory sharing with no loss of the CPU time
- Diverse functions including virtual screen , panning , scrolling , contrast control and alternating signal generator
- Support software 16 gray levels
-
Universal Asynchronous Receiver/Transmitter (UART)
- Full-duplex operation
- Baud rate generator with DPLL
- Standard baud rates of 600 bps to 115.2 kbps
- Direct glueless support of IrDA physical layer protocol
- Two sets of I/Os (TX,RX) for two independent devices
- Serial Peripheral Interface (SPI)
- Master and slave modes
- 5 serial signals including enable and data-ready
- One stage buffer for transmitter and receiver for continuous data exchange
- Programmable data length from 7-bit to 16-bit
- Memory configuration
- Three kinds of bank for program, data and interrupts
- 12-bit bank register supports up to 44M bytes
- 6 programmable chip-selects with 4 modes
- Maximum single device of 16M bytes at
- General-Purpose I/O (GPIO) ports
- 48 multiplexed CMOS bidirectional bit programmable I/Os
- Hardware de-bounce option for Port-A
- Bit programmable pull-up for input pins
- Bit programmable pull-up/down and open-drain/CMOS for Port-C
- Programmable Watchdog Timer (WDT)
- Timer/Counter
- Two 8-bit timer, one can be a 16-bit event counter
- One 8-bit Base timer with 5 coexistent interrupt time settings
- Three clocking outputs
- Clock sources including Timer0/1, baud rate generator
- 11 prioritized interrupts with dedicated exception vectors
- External interrupt (edge triggered)
- TIMER0 interrupt
- TIMER1 interrupt
- BASE timer interrupt
- PORTA interrupt (transition triggered)
- DAC reload interrupt
- LCD frame interrupt
- SPI interrupt (x2)
- UART interrupts (x2)
- Dual clock sources with warm-up timer
- Low frequency crystal oscillator (OSCX) 32768 Hz
- RC oscillator (OSC) 500K ~ 4M Hz
- High frequency crystal/resonator oscillator (Bonding option) 455K~4M Hz
- Direct Memory Access (DMA)
- Block-to-Block transfer
- Block to Single port
- Programmable Sound Generator (PSG)
- Two channels with three playing modes
- Tone/noise generator
- 16-level volume control
- 8-bit PWM DAC for speech/voice
- Two dedicated outputs for directly driving and large current
- Three power down modes
- WAI0 mode
- WAI1 mode
- STP mode
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